1. Field of the Invention
The present invention relates generally to a scribe line structure, and more specifically to a scribe line structure capable of preventing dicing cracks.
2. Description of the Prior Art
The manufacturing flow of the integrated circuit can be mainly distinguished into three stages as follows: (1) the manufacturing of the substrate, (2) the fabrication of the integrated circuit on the substrate, and (3) the cutting, electric testing, sorting, and packaging of the integrated circuit. When fabricating the integrated circuit on the substrate, the whole substrate is divided uniformly into mail repetitive dies, and the adjacent dies are separated by scribe lines. The cutting step of the integrated circuit utilizes a cutter to cut the substrate into individual dies along the scribe lines.
In recent years, the high integration semiconductor process with an inter-metal dielectric layer collocated by the dual damascene technology and the use of low dielectric materials is the most popular metal interconnect technology to date. Due to the low resistance of copper, and the low dielectric material, the RC delay between the metal wires is greatly reduced. However, for achieving low dielectric property, many of low dielectric materials have loose and weak mechanical strength structures, and are fragile. Therefore a chip crack often occurs from lateral cutting stress while performing wafer dicing. The chip crack damages the die seal ring region of the wafer that protects the die region and induces metal layer delamination. This causes high early failure rate in products, thereby reducing yield in subsequent electric test processes.